Debug Register Access

1. Introduction

This document describes how to read and write registers directly in hardware.

2. The tool

To support the register access the tool 'dbgreg' can be used.

Execute to see the help:

$ dbgreg -h
dbgreg - Register access debug tool


Usage:
  dbgreg [options] miim|sw [c22|c45] (<PORT>[:<MMD>]:<ADDR>[=VAL])...

Options:
  -h --help                  Show this screen.
  -d --device <URL>          IP based terminal device to connect to.
                             Ex: termhub://10.0.0.2:4000

Command details:
  Do a MIIM or Switch read or write request.
  miim: MIIM register access option.
  sw  : Switch register access option.
  c22 : Clause 22 MIIM access.
  c45 : Clause 45 MIIM access.
  PORT: 0-based switch port number.
  MMD : MMD (8 bits) for clause 45 access.
  ADDR: Register address (5/16/32 bits for c22/c45/switch access)
  VAL : Register value for write operation (16/32 bits for MIIM/switch access)

Key word 'miim' means PHY register access.
Key word 'sw' means Switch register access.
If [=VAL] is present it is register write otherwise it is register read.

3. Access to PHY register.

Reading registers in the PHY can be done like this:
The PHY is supporting Clause 22 registers.
The Port number is 1.
The register is 0.

Command:

$ dbgreg -d termhub://10.205.27.92:4113 miim c22 rd 1:0
mup1ct  coap post /dbg/reg --content-type 60 --accept 60
Status: 0, stderr: RESPONSE-CODE: class 2 detail 5 Success Content, got 14 bytes

                  Value              Value   Value
Oper  Port  Addr  15     8.7      0  Hex     Decimal
RD    1     0x00  00010001.01000000  0x1140  4416

The register content is 4416 or 0x1140.

4. Access to SWITCH register.

4.1. Calculating Register address on LAN969X

In order to calculate register offsets, information from some code source files is required. The files can be found here:

https://github.com/microchip-ung/mesa/tree/master/base/fa

In file 'vtss_fa_cil.h' this function is defined:

static inline u32 __ioreg(int t, int o, int gi, int gw, int ri, int rw, int gc, int rc)
{
    return (t + (o) + ((gi) * (gw)) + (ri) + (rw));
}

It is calculating the register offset based on a parameter set, that is given by macro’s defined in 'vtss_fa_regs.h'.

Example is register DEVCPU_GCB:CHIP_REGS:CHIP_ID
The parameter set for '__ioreg()' is given by this macro:

#define VTSS_DEVCPU_GCB_CHIP_ID   __REG(VTSS_TO_DEVCPU_GCB,0,0,0,0,0,1,1)

This code is calculating the result offset = '8404992'

u32 offset = __ioreg(VTSS_DEVCPU_GCB_CHIP_ID);

To calculate offsets to any register, information and macro’s can be found in 'vtss_fa_regs.h'.

4.2. Reading the Chip ID register on LAN969X.

Reading registers in the SWITCH can be done like this:
The register is '8404992' (DEVCPU_GCB:CHIP_REGS:CHIP_ID).

Command:

$ dbgreg -d termhub://10.205.27.92:4101 sw 8404992
mup1ct  coap post /dbg/reg --content-type 60 --accept 60
Status: 0, stderr: RESPONSE-CODE: class 2 detail 5 Success Content, got 18 bytes

                  Value                                Value       Value
Oper  Address     31    24.23    16.15     8.7      0  Hex         Decimal
RD    0x00804000  00001001.01101001.10110100.01000101  0x0969B445  157922373

The DEVCPU_GCB:CHIP_REGS:CHIP_I register content is 157922373 or 0x969B445.