USXGMII support on LAN969x

This page describes how to enable single-lane USXGMII on LAN969x.

1. Overview

USXGMII support is already part of the network driver and the SerDes driver. But this needs to be enabled through the device tree.

Unlike QUSXGMII on Sparx5, which muxes four sub-ports onto a single SerDes lane, single-lane USXGMII gives one port the whole lane. Use it to drive a single 10G-class port to a multirate multigig Cu PHY, e.g. a Marvell AQR113, over one 10.3125 Gbit/s SerDes lane, instead of muxing four PHY channels.

single-lane USXGMII is supported on LAN969x only. Sparx5 has an RTL erratum that makes single-mode USXGMII unusable, so on Sparx5 the USXGMII PCS/ANEG hardware only works in the 4-port muxed QXGMII mode described in QUSXGMII on Sparx5.

First it is required to have a PHY that supports USXGMII, in our example we use a board with a Marvell AQR113 Cu PHY.

This change adds the PHY address:

&mdio3 {
    status = "okay";
    phy0_ext: ethernet-phy@0 {
        reg = <0>;
    };
};

If the PHY needs a post-reset delay before it answers MDIO, add the property "reset-post-delay-us" to the MDIO bus node.

Now that the PHY is defined under the mdio bus we can update the network interface to use it:

port16: port@16 {
   reg = <16>;
   microchip,bandwidth = <10000>;
   phys = <&serdes 20>;
   phy-handle = <&phy0_ext>;
   phy-mode = "usxgmii";
   managed = "in-band-status";
};

It is important to note that the interface is set to be "usxgmii" as this describes which interface is used between the PHY and the MAC. The port must map to a 10G-class SerDes lane; on LAN969x every lane is 10G-class.

The PHY negotiates its own link rate — 10 Mbit/s, 100 Mbit/s, 1 Gbit/s, 2.5 Gbit/s, 5 Gbit/s, or 10 Gbit/s — and reports it to the MAC in-band, which is why the port requires managed = "in-band-status".