LAN966x FLEXCOM

SoC Resources

LAN966X SoC have 5 FLEXCOMs(Flexible Serial Communication Controller). Each flexcom supports three serial communication protocols that includes

  1. USART(Universal Synchronous Asynchronous Receiver Transceiver). Refer USART documentation

  2. SPI(Serial Peripheral Interface). Refer SPI documentation

  3. TWI(Two-wire Interface) or I2C(Inter Integrated Circuit). Refer TWI documentation

Each flexcom has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These chip-selects can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured.

Kernel configurations

Following kernel config options should be enabled to use LAN966x Flexcom interface:

  • CONFIG_MFD_ATMEL_FLEXCOM - Flexcom driver config option.

Devicetree Configuration

Following configurations are required to define a flexcom in device tree:

  • compatible string must be set to atmel,sama5d2-flexcom or set to microchip,lan966x-flexcom in case flexcom chip-select configurations are required.

  • Flexcom reg property must be set with register address and length. Refer table below:

FLEXCOM ID Flexcom base registers map

flx0

<0xe0040000 0x100>

flx1

<0xe0044000 0x100>

flx2

<0xe0060000 0x100>

flx3

<0xe0064000 0x100>

flx4

<0xe0070000 0x100>

  • clocks property must be set to <&clks GCK_ID_FLEXCOMx> where x is flexcom ID.

  • #address-cells must be set to 1.

  • #size-cells must be set to 1.

  • ranges must be set to one range for the full I/O register region.

  • Optional flexcom chip-select configurations: In order to map flexcom USART cts, rts lines or flexcom SPI cs0, cs1 lines to flexcom shared pins, use below properties:

    • Append flexcom shared register address and length to reg property. Refer table below:

    • microchip,flx-shrd-pins - Specify the flexcom shared pins to be mapped to chip-select line. Possible flexcom shared pins are [0-20].

    • microchip,flx-cs - Specify chip-selects to be configured.

      • 0 for cts line in USART mode, cs0 in SPI mode.

      • 1 for rts line in USART mode, cs1 in SPI mode.

FLEXCOM ID Flexcom shared registers map

flx0

<0xe2004168 0x8>

flx1

<0xe2004170 0x8>

flx2

<0xe2004178 0x8>

flx3

<0xe2004180 0x8>

flx4

<0xe2004188 0x8>

References

Example

Following example shows how a flexcom should be defined in device tree.

Example to configure flexcom2 in TWI mode:

dtsi file:

flx2: flexcom@e0060000 {
        compatible = "atmel,sama5d2-flexcom";
        reg = <e0060000 0x100>;
        clocks = <&clks GCK_ID_FLEXCOM2>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 e0060000 0x800>;
        status = "disabled";
};

dts file:

&flx2 {
        atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
        status = "okay";
};

Example to configure flexcom3 in SPI mode and map cs0 to flexcom shared pin 4:

dtsi file:

flx3: flexcom@e0064000 {
        compatible = "microchip,lan966x-flexcom";
        reg = <0xe0064000 0x100>,
              <0xe2004180 0x8>;
        clocks = <&clks GCK_ID_FLEXCOM3>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0xe0064000 0x800>;
        status = "disabled";
};

dts file:

&flx3 {
        atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
        microchip,flx-shrd-pins = <4>;
        microchip,flx-cs = <0>;
        status = "okay";
};