QUSXGMII support on Sparx5

This page describes on how to enable QUSXGMII on Sparx5.

1. Overview

The QUSXGMII support is already part of the network driver and the serdes driver. But this needs to be enabled through the device tree.

First it is required to have a PHY that supports the QUSXGMII, in our example we use pcb135 which was modified by adding a MaxLinear GPY241 4x 2.5G Cu PHY.

This change adds the PHY addresses:

&mdio3 {
    status = "okay";
    phy0_ext: ethtrnet-phy@0 {
        reg = <0>;
    };
    phy1_ext: ethtrnet-phy@1 {
        reg = <1>;
    };
    phy2_ext: ethtrnet-phy@2 {
        reg = <2>;
    };
    phy3_ext: ethtrnet-phy@3 {
        reg = <3>;
    };

On our board it was required to add the property "reset-post-delay-us" to node "mdio0" because apparently these PHYs are not getting out of reset directly but it requires a delay before they can be accessed.

Now that the PHYs are defined under the mdio bus we can update the network interfaces to start to use them:

port8: port@8 {
   reg = <8>;
   microchip,bandwidth = <2500>;
   phys = <&serdes 25>;
   phy-handle = <&phy1_ext>;
   phy-mode = "10g-qxgmii";
   managed = "in-band-status";
};
port24: port@24 {
   reg = <24>;
   microchip,bandwidth = <2500>;
   phys = <&serdes 25>;
   phy-handle = <&phy2_ext>;
   phy-mode = "10g-qxgmii";
   managed = "in-band-status";
};
port40: port@40 {
   reg = <40>;
   microchip,bandwidth = <2500>;
   phys = <&serdes 25>;
   phy-handle = <&phy3_ext>;
   phy-mode = "10g-qxgmii";
   managed = "in-band-status";
};
port56: port@56 {
   reg = <56>;
   microchip,bandwidth = <2500>;
   phys = <&serdes 25>;
   phy-handle = <&phy0_ext>;
   phy-mode = "10g-qxgmii";
   managed = "in-band-status";
};

It is important to note that the interface is set to be "10g-qxgmii" as this describe which interface is used between the PHY and the MAC.